Schottky Diodes Including Polysilicon Having Low Barrier Heights

ABSTRACT

Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.

CLAIM OF PRIORITY

The present application is a divisional of and claims priority fromco-pending U.S. application Ser. No. 12/479,376, filed Jun. 3, 2009, nowU.S. Pat. No. ______, which is assigned to the assignee of the presentapplication, the disclosure of which is hereby incorporated herein byreference as if set forth fully.

STATEMENT OF U.S. GOVERNMENT INTEREST

This invention was made with Government support under ONR/DARPA ContractNo. 05-C-0202. The Government has certain rights in the invention.

FIELD

The present invention generally relates to semiconductor devices and,more particularly, to Schottky diodes and methods of fabricating thesame.

BACKGROUND

High voltage silicon carbide (SiC) devices can handle voltages aboveabout 600V or more. Such devices may handle as much as about 100 amps ormore of current, depending on their active area. High voltage SiCdevices have a number of important applications, particularly in thefield of power conditioning, distribution and control. High voltagesemiconductor devices, such as Schottky diodes, MOSFETs, GTOs, IGBTs,BJTs, etc., have been fabricated using silicon carbide.

Schottky barrier diodes are used extensively as output rectifiers inswitching-mode power supplies and in other high-speed power switchingapplications, such as motor controls, for carrying large forwardcurrents and supporting large reverse blocking voltages. Diodes exhibitlow resistance to current flow in a forward direction and a very highresistance to current flow in a reverse direction. A Schottky barrierdiode produces rectification as a result of nonlinear unipolar currenttransport across a metal semiconductor contact.

Silicon carbide (SiC) Schottky diodes are a promising technology becausesuch devices can provide a low forward voltage drop, high breakdownvoltage, and fast switching speed with essentially no reverse recoverycurrent. However, the operational characteristics of a Schottky diodecan depend heavily on the type of metal used for the Schottky contact.

The power dissipated by a Schottky diode depends on the forward voltagedrop and the reverse leakage current, both of which should be as low aspossible. The forward voltage drop and the reverse leakage current arerelated to the barrier height of the Schottky contact, i.e., themagnitude of the potential barrier between the metal and semiconductorregions of the Schottky contact.

A low barrier height metal will have a low forward voltage drop and alarge reverse leakage current. Conversely, a high barrier height metalwill have a larger forward voltage drop and a smaller reverse leakagecurrent. Therefore, it is desirable to have a Schottky diode whichexhibits the forward characteristics of a small barrier height metal andthe reverse characteristics of a large barrier height metal. A trenchtype Schottky diode can be configured to partially satisfy theseconflicting design criteria by using lines of high barrier metals topinch-off or electrically shield intervening trenched lines of lowbarrier metals. Although such trench type Schottky diodes may provideimproved forward and reverse operational characteristics, theirfabrication cost may be increased by the processes needed to form thetrenches and high/low barrier metal lines, and their forward and reversecharacteristics can be limited by the trench and high/low metal linefeature sizes that are obtainable.

SiC PIN diodes are very attractive for RF limiter applications. Inparticular, the high breakdown strength and high thermal conductivity ofSiC may enable much higher RF power levels and faster switching speedsthan may have been possible using silicon (Si) or gallium arsenide(GaAs) technologies. In these applications, a Schottky diode is commonlyused to rectify the RF signal and produce a bias current for the PINdiode, which will limit the RF signal to acceptable levels. The barrierheight of the Schottky diode used in these applications should berelatively low to rectify low-level RF signals. Many applicationsrequire a barrier height of 0.5 eV or less. However, most commonly usedmaterials, such as chromium (Cr) and Titnanium (Ti) only provide barrierheights of about 0.8 eV or higher on SiC.

SUMMARY

Some embodiments of the present invention provide hybrid semiconductordevices including a PIN diode portion and a Schottky diode portion. ThePIN diode portion is provided on a semiconductor substrate and has ananode contact on a first surface of the semiconductor substrate. TheSchottky diode portion is also provided on the semiconductor substrateand includes a polysilicon layer on the semiconductor substrate and thepolysilicon layer acts as a Schottky contact.

In further embodiments of the present invention, the semiconductorsubstrate may include Gallium Nitride (GaN).

In still further embodiments of the present invention, the semiconductorsubstrate may include silicon carbide (SiC). In certain embodiments, theSiC substrate may be a semi-insulating SiC substrate.

In some embodiments of the present invention, the polysilicon layer maybe an N-type polysilicon layer.

In further embodiments of the present invention, a SiC drift layer maybe provided on the SiC substrate. A P-type SiC layer may be provided onthe SiC drift layer. The SiC drift layer and the P-type SiC layer maydefine a trench that extends through the P-type SiC layer and exposesthe SiC layer. The polysilicon layer may be on the exposed portion ofthe SiC layer. The ohmic contact may be on the polysilicon layer and theanode contact of the PIN diode portion may be on the P-type SiC layer.The SiC layer may be an insulating SiC layer.

In still further embodiments of the present invention, the anode contactof the PIN diode portion may be an ohmic contact including aluminum,titanium and/or nickel.

In some embodiments of the present invention, the trench may be a firsttrench. An N-type SiC layer may be provided on the SiC substrate betweenthe SiC substrate and the SiC layer. The SiC layer and the N-type SiClayer may define a second trench that extends through the SiC layer andexposes the N-type SiC layer. An ohmic contact may be provided on theexposed portion of the N-type SiC layer.

In further embodiments of the present invention, the device may have abarrier height of less than about 0.8 eV to about 0.3eV.

In still further embodiments of the present invention, the device may bestable at operating temperatures up to about 250° C.

Some embodiments of the present invention provide Schottky diodesincluding a drift layer on a first surface of a semiconductor substrate,a polysilicon layer on the drift layer and an anode contact on thepoly-silicon layer.

In further embodiments of the present invention, the drift layer mayinclude a silicon carbide (SiC) drift layer and the semiconductorsubstrate may be a SiC substrate.

In still further embodiments of the present invention, the polysiliconlayer may be an N-type polysilicon layer. A cathode contact may beprovided on a second surface of the semiconductor substrate, oppositethe first surface of the substrate. In certain embodiments, the diodemay be a junction barrier Schottky (JBS) diode. In these embodiments,the diode may further include a plurality P-type regions in the SiCdrift layer. The anode contact may form a Schottky junction with theexposed portions of the SiC drift layer and an ohmic contact with theplurality of P-type regions.

In some embodiments of the present invention, the drift layer may be alayer including gallium nitride (GaN) and the semiconductor substratemay be a GaN substrate. The diode may further include a cathode contacton the layer including GaN that is spaced apart from the polysiliconlayer and the anode contact.

In further embodiments of the present invention, the layer including GaNmay include aluminum gallium nitride (AlGaN).

Still further embodiments of the present invention provide a Schottkydiode including a drift layer on a first surface of a semiconductorsubstrate; a barrier layer on the drift layer; and an anode contact onthe barrier layer. The barrier layer provides a diode having a barrierheight of from about 0.2eV to about 0.8eV. The barrier height may be 0.5eV or less, 0.4 eV or less, 0.3 eV or less or from about 0.2 eV about0.5 eV.

Although embodiments of the present invention are primarily discussedabove with respect to device embodiments, related methods of fabricatingthese devices are also provided herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this application, illustrate certain embodiment(s) of theinvention. In the drawings:

FIG. 1 is a cross section illustrating a hybrid semiconductor device inaccordance with some embodiments of the present invention.

FIGS. 2 and 3 are graphs illustrating performance characteristics ofhybrid devices in accordance with some embodiments of the presentinvention.

FIGS. 4A through 4F are cross sections illustrating processing steps inthe fabrication of hybrid semiconductor devices in accordance with someembodiments of the present invention.

FIGS. 5 through 7 are cross sections illustrating diodes includingpolysilicon layers in accordance with some embodiments of the presentinvention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Embodiments of the present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the invention are shown. This invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. Rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art.Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”“comprising,” “includes” and/or “including” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present. Itwill also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,”“lateral,” “vertical,” “beneath,” “over,” etc., may be used herein todescribe a relationship of one element, layer or region to anotherelement, layer or region as illustrated in the figures. It will beunderstood that these terms are intended to encompass differentorientations of the device in addition to the orientation depicted inthe figures.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention.The thickness of layers and regions in the drawings may be exaggeratedfor clarity. Additionally, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments of theinvention should not be construed as limited to the particular shapes ofregions illustrated herein but are to include deviations in shapes thatresult, for example, from manufacturing. For example, an implantedregion illustrated as a rectangle will, typically, have rounded orcurved features and/or a gradient of implant concentration at its edgesrather than a discrete change from implanted to non-implanted region.Likewise, a buried region formed by implantation may result in someimplantation in the region between the buried region and the surfacethrough which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of the invention.

Some embodiments of the invention are described with reference tosemiconductor layers and/or regions which are characterized as having aconductivity type such as N-type or P-type, which refers to the majoritycarrier concentration in the layer and/or region. Thus, N-type materialhas a majority equilibrium concentration of negatively chargedelectrons, while P-type material has a majority equilibriumconcentration of positively charged holes. Some material may bedesignated with a “+” or “−” (as in n⁺, p⁺, p⁻, n⁺⁺, n⁻⁻, p⁺⁺, p⁻⁻, orthe like), to indicate a relatively larger (“+”) or smaller (“−”)concentration of majority carriers compared to another layer or region.However, such notation does not imply the existence of a particularconcentration of majority or minority carriers in a layer or region.

As discussed above, SiC PIN diodes are very attractive for RF limiterapplications. In particular, the high breakdown strength and highthermal conductivity of SiC may enable much higher RF power levels andfaster switching speeds than may have been possible using silicon (Si)or gallium arsenide (GaAs) technologies. In these applications, aSchottky diode is commonly used to rectify the RF signal and produce abias current for the PIN diode, which will limit the RF signal toacceptable levels. The barrier height of the Schottky diode used inthese applications should be relatively low to rectify low-level RFsignals. Many applications require a barrier height of 0.5 eV or less.However, most commonly used materials, such as chromium (Cr) andTitnanium (Ti) only provide barrier heights of about 0.8 eV or higher onSiC. Barrier heights of 0.8 eV may only detect larger signals.Accordingly, there is a need for devices that can detect relativelysmaller signals on SiC.

Thus, according to some embodiments of the present invention, RF diodesare provided that have the capability of detecting smaller signals onSiC. In particular, as will be discussed further herein, devices inaccordance to some embodiments of the present invention may have barrierheights significantly less than 0.8 eV. For example, in someembodiments, the barrier height may be 0.5 eV or less. In someembodiments, the barrier height may be 0.4 eV or less, 0.3 eV or less,or from about 0.2 eV to about 0.5 eV without departing from the scope ofthe present invention. In some embodiments of the present invention,these RF diodes include N-type polysilicon in a Schottky diode on SiC.Devices in accordance with some embodiments of the present invention mayprovide RF diodes having low barrier heights, robust device performancedue to the polysilicon contact on SiC, improved avalanche capability andhigh temperature capability as will be discussed further herein withrespect to FIGS. 1 through 7.

Exemplary embodiments of the present invention will now be discussedwith respect to FIGS. 1 through 7. Referring first to FIG. 1, a hybridsemiconductor device 100 in accordance with some embodiments of thepresent invention will be discussed. As illustrated in FIG. 1, an N⁺drift layer 112 is provided on a substrate 110. The substrate 110 may bea semi-insulating silicon carbide (SiC) substrate, that may be, forexample, the 4H polytype of silicon carbide. Other silicon carbidecandidate polytypes may include the 3C, 6H, and 15R polytypes. The term“semi-insulating” is used descriptively herein, rather than in anabsolute sense. In some embodiments of the present invention, thesilicon carbide bulk crystal may have a resistivity equal to or higherthan about 1×10⁵ Ω-cm at room temperature.

Silicon carbide has a much closer crystal lattice match to Group IIInitrides than does sapphire (Al₂O₃), which may be a common substratematerial for Group III nitride devices. The closer lattice match mayresult in Group III nitride films of higher quality than those generallyavailable on sapphire. Silicon carbide also has a relatively highthermal conductivity, and as such, the total output power of Group IIInitride devices formed on silicon carbide may not be as limited bythermal dissipation of the substrate as similar devices formed onsapphire and/or silicon. Also, semi-insulating silicon carbidesubstrates may provide for device isolation and reduced parasiticcapacitance. Exemplary SiC substrates that may be used in someembodiments of the present invention are manufactured by, for example,Cree, Inc., of Durham, N.C., the assignee of the present invention, andmethods for producing such substrates are described, for example, in U.S. Pat. Nos. Re. 34,861; 4,946,547; 5,200,022; and 6,218,680, thedisclosures of which are incorporated by reference herein in theirentireties. Similarly, techniques for epitaxial growth of Group IIInitrides have been described in, for example, U. S. Pat. Nos. 5,210,051;5,393,993; 5,523,589; and 5,292,501, the disclosures of which are alsoincorporated by reference herein in their entireties.

The N⁺ drift layer 112 may be an N⁺ SiC layer having a thickness of fromabout 0.1 μm to about 10 μm. The N⁺ drift layer 112 may have a carrierconcentration of from about 1.0×10¹⁴cm⁻³ to about 5.0×10¹⁷cm⁻³. Asfurther illustrated in FIG. 1, an insulating SiC layer (i-SiC) 114 isformed on the N⁺ drift layer 112. In some embodiments of the presentinvention, the insulating SiC layer 114 may be lightly doped, forexample, less then about 5.0×10¹⁴cm⁻³. In some embodiments of thepresent invention, insulating SiC layer 114 may be doped with, forexample, Vanadium (V) or Iron (Fe). The insulating SiC layer 114 mayhave a thickness of from about 0.1 μm to about 10 μm.

A P-type SiC layer 116 is provided on the insulating SiC layer 114. TheP-type SiC layer 116 may include 6H, 4H, 15R or 3C polytype siliconcarbide. In some embodiments, the P-type SiC layer is a P⁺ SiC layerhaving a carrier concentration of from about 1.0×10¹⁸CM⁻³ to about1.0×10²⁰cm⁻³. Suitable dopants include aluminum (Al), boron(B) and/orgallium(Ga). The P-type SiC layer 116 may have a thickness of from about0.1 μm to about 2.0 μm. A P-type ohmic contact 133 including Al,Titanium (T) and/or Nickel (N) is provided on the P-type SiC layer 116and completes the PIN diode portion 103 of the hybrid device 100.

As further illustrated in FIG. 1, the insulating SiC layer 114 and theP-type SiC layer 116 define first and second trenches 160 and 161. Inparticular, the first trench extends through the P-type SiC layer 116and into the insulating SiC layer 114 from about 0.1 μm to about 5 μmexposing a surface of the insulating SiC layer 114. A polysilicon layer120 is provided on the exposed portion of the insulating SiC layer. Insome embodiments, the polysilicon layer 120 may be N⁺ polysilicon. ASchottky diode portion 105 is completed by providing a contact 130 onthe polysilicon layer 120. A Schottky contact is formed between thepolysilicon layer 120 and the insulating SiC layer 114. The contact 130can be any suitable Schottky metal, such as nickel (Ni), Titanium (Ti),Aluminum (Al) and Tungsten (W) without departing from the scope of thepresent invention.

The second trench extends through the P-type SiC layer 116 and theinsulating SiC layer 114 and exposes a surface of the N⁺ drift layer112. An N-type ohmic contact 135 is formed on the exposed surface of theN⁺ drift layer 112. The N-type ohmic contact may include, for example,Ni or polysilicon. Passive components of the device may be formed tocomplete the device using methods known to those having skill in the artand, therefore, details thereof will not be discussed further herein.

As discussed above, the presence of the polysilicon layer 120 in theSchottky portion 105 of the device may provide RF diodes that have thecapability of detecting smaller signals on SiC. In particular, hybriddevices in accordance with some embodiments of the present invention mayhave barrier heights significantly less than 0.8 eV, for example, 0.5 eVor less. As discussed above, some embodiments of the present inventionprovide RF diodes including N-type polysilicon in a Schottky diodeportion of the device on SiC. Devices in accordance with someembodiments of the present invention may provide RF diodes having lowbarrier heights, robust device performance due to the polysiliconcontact on SiC, improved avalanche capability and high temperaturecapability.

Exemplary forward and reverse IV characteristics for hybridsemiconductor devices in accordance with some embodiments of the presentinvention are illustrated in FIGS. 2 and 3. In particular, FIG. 2 is agraph illustrating forward IV characteristics of N⁺ polysilicon SiCSchottky diodes in accordance with some embodiments of the presentinvention. A voltage as low as 50 mV has been achieved which indicates alow Schottky barrier height. Similarly, FIG. 3 is a graph illustratingreverse IV characteristics of n⁺ polysilicon SiC Schottky diodes inaccordance with some embodiments of the present invention. A blockingvoltage of greater than about 40V was demonstrated with a low leakagecurrent.

Referring now to FIGS. 4A to 4E, processing steps in the fabrication ofhybrid semiconductor devices in accordance with some embodiments of thepresent invention will be discussed. Referring first to FIG. 4A, an N⁺drift layer 112 is formed on a substrate 110. The substrate 110 may be asemi-insulating silicon carbide (SiC) substrate, that may be, forexample, the 4H polytype of silicon carbide. Other silicon carbidecandidate polytypes may include the 3C, 6H, and 15R polytypes. The term“semi-insulating” is used descriptively herein, rather than in anabsolute sense. In some embodiments of the present invention, thesilicon carbide bulk crystal may have a resistivity equal to or higherthan about 1×10⁵ Ω-cm at room temperature.

The N⁺ drift layer 112 may be an N⁺ SiC layer and may be formed to havea thickness of from about 0.1 μm to about 10 μm. The N⁺ drift layer 112may be doped to have a carrier concentration of from about 1.0×10¹⁴CM³to about 5.0×10¹⁷cm⁻³. As further illustrated in FIG. 1, insulating SiClayer (i-SiC) 114 is formed on the N⁺ drift layer 112. In someembodiments of the present invention, insulating SiC layer 114 may bedoped with, for example, Vanadium (V) or Iron (Fe). The insulating SiClayer 114 may be formed to have a thickness of from about 0.1 μm toabout 10 μm.

A P-type SiC layer 116 is formed on the insulating SiC layer 114. TheP-type SiC layer 116 may include 6H, 4H, 15R or 3C polytype siliconcarbide. In some embodiments, the P-type SiC layer is P⁺ SiC layerhaving a carrier concentration of from about 1.0×10¹⁰cm⁻³ to about1.0×10²⁰cm⁻³. Suitable dopants include aluminum (Al), boron(B) and/orgallium(Ga). The P-type SiC layer 116 may have a thickness of from about0.1 μm to about 2 μm. In some embodiments, the insulating SiC layer 114may be lightly doped, for example, less than about 5.0×10¹⁴cm⁻³, n-typeor p-type.

Referring now to FIG. 4B, a mask 170 is formed on the P-type SiC layer116. The P-type SiC layer 116 and the insulating SiC layer 114 may bepatterned and etched using the mask 170. The mask 170 may include aphotoresist and/or a metal, and may be patterned using conventionalphotolithographic/liftoff techniques without departing from the scope ofthe present invention. In particular, the P-type SiC layer 116 and theinsulating SiC layer 114 are etched to form a first trench 160 asillustrated in FIG. 4C. As illustrated, the trench 160 extends throughthe P-type SiC layer 116 and into the insulating SiC layer 114 exposinga surface of the insulating SiC layer 114. In some embodiments, thetrench 160 may extend from about 0.1 μm to about 5 μm into theinsulating SiC layer 114. The etch time may be adjusted such that theprocess will terminate when the trench 160 has extended into insulatingSiC layer 116 in the acceptable range. The mask 170 may be removed.

A second mask 171 is formed on the P-type SiC layer 116 and theinsulating SiC layer 114 as illustrated in FIG. 4D. The insulating SiClayer 114 and the N⁺ drift layer 112 may be patterned and etched usingthe mask 171. The mask 171 may include a photoresist and/or a metal, andmay be patterned using conventional photolithographic/liftoff techniqueswithout departing from the scope of the present invention. Inparticular, the insulating SiC layer 114 and the N⁺ drift layer 112 maybe etched to form the second trench 161 as illustrated in FIG. 4E. Asillustrated, the trench 161 extends through the insulating SiC layer 114exposing a surface of the N⁺ drift layer 112. In some embodiments, thetrench 161 may extend from about 0.1 μm to about 2.0 μm into N⁺ driftlayer 112. The etch time may be adjusted such that the process willterminate when the trench 161 has extended into N⁺ drift layer 112 inthe acceptable range. The mask 171 may be removed.

As illustrated in FIG. 4F, contacts may be formed to complete the PINdiode portion 103 and the Schottky diode portion 105 of the hybriddevice 100. In particular, metal or polysilicon may be deposited on theN⁺ drift layer 112 to form an N-type ohmic contact 135 on the exposedsurface of the N⁺ drift layer 112. The N-type ohmic contact 135 mayinclude, for example, Ti, Ni, W or polysilicon. Similarly, metal may bedeposited on the P-type SiC layer 116 to form a P-type ohmic contact 133including Al, T and/or N and completes the PIN diode portion 103 of thehybrid device 100.

As further illustrated in FIG. 4F, a polysilicon layer 120 may bedeposited on the exposed portion of the insulating SiC layer 114 using,for example, low-pressure chemical vapor deposition (LPCVD). In someembodiments, the polysilicon layer 540 may be N⁺ polysilicon. Thepolysilicon layer 120 may be patterned to remain on the exposed portionof the insulating SiC layer 114 as illustrated in FIG. 4F. Metal isdeposited on the polysilicon layer 120 to form an ohmic contact 130 onthe polysilicon layer 120. The contact 130 can be any suitable metal,such as Al, Ni, Ti and W without departing from the scope of the presentinvention. In some embodiments of the present invention, the Schottkycontact is non-ohmic. The formation of the contact 130 on thepolysilicon layer 120 completes the formation of the Schottky portion105 of the hybrid device 100.

Passive components of the device may be formed to complete the deviceusing methods known to those having skill in the art and, therefore,details thereof will not be discussed further herein.

As discussed above, the presence of the polysilicon layer 120 in theSchottky portion 105 of the device may provide RF diodes that have thecapability of detecting smaller signals on SiC. In particular, hybriddevices in accordance with some embodiments of the present invention mayhave barrier heights significantly less than 0.8 eV, for example, 0.5 eVor less. As discussed above, some embodiments of the present inventionprovide RF diodes including N-type polysilicon in a Schottky diodeportion of the device on SiC. Devices in accordance with someembodiments of the present invention may provide RF diodes having lowbarrier heights, robust device performance due to the polysiliconcontact on SiC, improved avalanche capability and high temperaturecapability.

Referring now to FIGS. 5 through 7, embodiments of various Schottkydiode structures including polysilicon will be discussed. In particular,embodiments of the present invention discussed above with respect toFIGS. 1 through 4F are directed to a hybrid semiconductor device 100including both a PiN diode portion and a Schottky diode portion on ashared substrate. It will be understood that embodiments of the presentinvention are not limited to this configuration. For example,polysilicon may be used in Schottky diodes and may provide similaradvantages as those discussed above with respect to the hybridsemiconductor device.

Referring now to FIG. 5, a cross section of a Schottky diode inaccordance with some embodiments of the present invention will bediscussed. A SiC drift layer 514 is provided on a SiC semiconductorsubstrate 510. A passivation layer 580 is provided on the SiC driftlayer 514. A polysilicon layer 540 is provided in an opening in thepassivation layer 580 such that the polysilicon layer is provided onboth a surface of the SiC drift layer 514 exposed by the trench and onthe passivation layer 580. In some embodiments, the polysilicon layer540 may be N⁺ polysilicon. An anode contact 533 may be provided on thepolysilicon layer 540 and a cathode contact 537 may be provided on thesubstrate 510 to complete the Schottky diode of FIG. 5. The presence ofthe polysilicon layer 540 in FIG. 5 may provide improved characteristicsof the Schottky diode as discussed above with respect to the hybridsemiconductor device.

Referring now to FIG. 6, a cross section of a junction barrier Schottky(JBS) diode will be discussed. The JBS diode of FIG. 6 is very similarto the diode illustrated in FIG. 5, except a plurality of junctions areprovided in the SiC drift layer 614. These junctions are provided toprovide devices exhibiting relatively lower leakage currents. Thepresence of the polysilicon layer 640 in FIG. 6 may provide improvedcharacteristics of the Schottky diode as discussed above with respect tothe hybrid semiconductor device.

As discussed above, embodiments of the present invention are not limitedto the use of SiC. Different materials may be used without departingfrom the scope of the present invention. Referring to FIG. 7, a layerincluding gallium nitride (GaN) 713, for example, aluminum galliumnitride (AlGaN), may be provided on a GaN substrate 711. A passivationlayer 780 may be provided on the layer including GaN 713 and an openingmay be defined therein exposing a surface of the layer including GaN713. A polysilicon layer 740, for example, N⁺ polysilicon, may beprovided in the opening such that the polysilicon layer 740 is providedon the exposed portion of the layer including GaN 713 and thepassivation layer 780. An anode contact 733 is provided on thepolysilicon layer 740 and a cathode contact is provided on the layerincluding GaN 413 to complete the Schottky diode. The presence of thepolysilicon layer 740 in FIG. 7 may provide improved characteristics ofthe Schottky diode as discussed above with respect to the hybridsemiconductor device.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

1. A Schottky diode, comprising: a drift layer on a first surface of asemiconductor substrate; a polysilicon layer on the drift layer; and ananode contact on the poly-silicon layer.
 2. The diode of claim 1,wherein the drift layer comprises a silicon carbide (SiC) drift layerand the semiconductor substrate comprises a SiC substrate.
 3. The diodeof claim 2, wherein the polysilicon layer comprises N-type polysilicon.4. The diode of claim 3, further comprising a cathode contact on asecond surface of the semiconductor substrate, opposite the firstsurface of the substrate.
 5. The diode of claim 4, wherein the diodecomprises a junction barrier Schottky (JBS) diode and wherein the diodefurther comprises a plurality P-type regions in the SiC drift layer andwherein the anode contact forms a Schottky junction with the exposedportions of the SiC drift layer and an ohmic contact with the pluralityof P-type regions.
 6. The diode of claim 1, wherein the drift layercomprises a layer including gallium nitride (GaN) and the semiconductorsubstrate comprises GaN, the diode further comprising a cathode contacton the layer including GaN that is spaced apart from the polysiliconlayer and the anode contact.
 7. The diode of claim 6, wherein the layerincluding GaN comprises aluminum gallium nitride (AlGaN).
 8. A Schottkydiode, comprising: a drift layer on a first surface of a semiconductorsubstrate; a barrier layer on the drift layer; and an anode contact onthe barrier layer, wherein the barrier layer provides a diode having abarrier height of from about 0.2eV to about 0.8eV.
 9. The diode of claim8, where the barrier height is 0.5 eV or less.
 10. The diode of claim 9,wherein the barrier height is 0.4 eV or less.
 11. The diode of claim 10,wherein the barrier height is 0.3 eV or less.
 12. The diode of claim 8,wherein the barrier height is from about 0.2 eV to about 0.5 eV.